View DS3901E_862944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds3901 is a triple, 8-bit nonvolatile (nv) variable resistor. each of the resistors has two setting registers, which are selectable by software or by pin configura- tion. the selected register determines the value of the variable resistor. additionally, all three resistors have a high-impedance setting. resistor r0 has the additional flexibility of allowing an external shunt resistor to pro- vide increased dynamic range. internal address set- tings allow the ds3901 slave address to be programmed to one of 128 possible addresses. the ds3901 also features an optional password-protection scheme that allows the protection of sensitive data. applications optical transceivers optical transponders instrumentation and industrial controls rf power amps audio power-amp biasing replacement for mechanical variable resistors and dip switches features ? three 256-position linear digital resistors ? full-scale resistances 50k, 30k, 20k ? dual nv settings for each resistor ? low temperature-coefficient resistors ? i 2 c serial interface ? wide operating voltage (2.4v to 5.5v) ? two-level password write protection ? 232 bytes of user eeprom ? programmable slave address ? -40? to +95? operating temperature range ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ______________________________________________ maxim integrated products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc n.c. h2 l2 bk_sel add_sel sda scl top view h1 h0 l0 gnd n.c. dis tssop ds3901 + pin configuration rev 0; 4/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes lead-free package. ordering information typical operating circuit appears at end of data sheet. part temp range resistor values for r0, r1, and r2 pin- package DS3901E+ -40? to +95? 50k , 30k , 20k 14 tssop
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +95?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc, sda, scl relative to gnd .........-0.5v to +6.0v voltage on add_sel, bk_sel, dis relative to gnd .................-0.5v to (v cc + 0.5v), not to exceed +6.0v voltage on h0, h1, h2, l2, l0 relative to gnd........-0.5v to +6.0v maximum resistor current....................................................3ma operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature ....................................refer to ipc/jedec j-std-020 specification maximum switch current ......................................................3ma parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.4 5.5 v input logic 0 (sda, scl, add_sel) v il (note 1) -0.3 0.3 x v cc v input logic 1 (sda, scl, add_sel) v ih (note 1) 0.7 x v cc v cc + 0.3 v input logic 0 (bk_sel, dis) v il (note 1) -0.3 +0.8 v input logic 1 (bk_sel, dis) v ih (note 1) 2.0 v cc + 0.3 v voltage on resistor inputs h0, h1, l0, h2, l2 -0.3 +5.5 v switch current (l0_sw, hi-z0, hi-z1, hi-z2) i sw (note 2) 3 ma electrical characteristics (v cc = +2.4v to +5.5v, t a = -40 c to +95 c, unless otherwise noted.) parameter symbol conditions min typ max units standby current i stby (note 3) 250 a input leakage i l -1 +1 a v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v pulldown resistance (bk_sel) r bk 20 30 45 k ? pullup resistance (dis) r dis 20 30 45 k ? bk_sel pulse width 20 s
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom _____________________________________________________________________ 3 analog resistor characteristics (v cc = +2.4v to +5.5v, t a = -40 c to +95 c, unless otherwise noted.) parameter symbol conditions min typ max units resistor tolerance t a = +25 c -20 +20 % r0, r2 242 500 position 00h resistance r1 149 250 ? r0 50 r1 30 position ffh resistance r2 20 k ? switch resistance r l0_sw at 3ma 150 ? absolute linearity (note 4) -0.75 +0.75 lsb relative linearity (note 5) -0.75 +0.75 lsb temperature coefficient position ffh (notes 2, 6) 50 ppm/ c hi-z resistor leakage i rhiz h0, h1, h2, l0, or l2 = v cc -1 +1 a i 2 c characteristics (v cc = +2.4v to +5.5v, t a = -40 c to +95 c, unless otherwise noted. timing referenced to v il(max) and v ih(min) .) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s rise time of both sda and scl signals t r (note 8) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 8) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 s capacitive load for each bus line c b (note 8) 400 pf eeprom write time t w (note 9) 10 ms input capacitance c i 5pf startup time t st 0.3 2 ms
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 4 _____________________________________________________________________ note 1: all voltages referenced to ground. note 2: guaranteed by design. note 3: i stby specified for the inactive state measured with sda = scl = v cc , add_sel = gnd, bk_sel, dis, h0, h1, h2, l2, l0 floating. note 4: absolute linearity is the deviation of a measured resistor-setting value from the expected value at each particular resistor setting. expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. note 5: relative linearity is the deviation of the step size change between two lsb settings from the expected step size. the expected lsb step size is the slope of the straight line from measured minimum position to measured maximum position. note 6: see the typical operating characteristics . note 7: timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard mode. note 8: cb total capacitance of one bus line in picofarads. note 9: eeprom write begins after a stop condition occurs. nonvolatile memory characteristics (v cc = +2.4v to +5.5v.) parameter symbol condition min typ max units eeprom write cycles t a =+ 70 c (note 2) 50,000 typical operating characteristics (v cc = +3.3v, t a = +25 c, unless otherwise noted.) 165 171 169 167 173 175 177 179 181 183 185 -40 14 -13 416895 supply current vs. temperature ds3901 toc01 temperature ( c) supply current ( a) add_sel = gnd sda = scl = v cc , all others are floating 110 130 140 150 160 170 180 190 200 2.400 3.175 3.950 4.725 5.500 supply current vs. supply voltage ds3901 toc02 supply voltage (v) supply current ( a) 120 add_sel = gnd sda = scl = v cc , all others are floating 175 180 185 190 195 200 205 0100 50 150 200 250 300 350 400 supply current vs. scl frequency ds3901 toc03 scl frequency (khz) supply current ( a) add_sel = gnd sda = scl = v cc , all others are floating 0 40 30 20 10 50 0 102 51 153 204 255 resistance vs. resistor setting ds3901 toc04 setting (dec) resistance (k ? ) r2 r1 r0 0 300 200 100 400 500 600 700 800 900 1000 0 102 51 153 204 255 temperature coefficient vs. resistor setting ds3901 toc05 setting (dec) temperature coefficient (ppm/ c) r0, -40 c to +25 c r1, -40 c to +25 c r2, -40 c to +25 c r0, +25 c to +95 c r1, +25 c to +95 c r2, +25 c to +95 c -13 7 12 2 -3 -8 -40 14 -13 41 68 95 change in resistance vs. temperature ds3901 toc06 temperature ( c) resistor change (%) resistor setting = 00h r1 r0 r2
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom _____________________________________________________________________ 5 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 c, unless otherwise noted.) -0.600 0.000 -0.200 -0.400 0.200 0.400 0.600 0800 1.000 1.200 1.400 -40 14 -13 416895 change in resistance vs. temperature ds3901 toc07 temperature ( c) resistor change (%) resistor setting = ffh r2 r1 r0 -0.10 -0.04 -0.06 -0.08 -0.02 0 0.02 0.04 0.06 0.08 0.10 2.400 3.175 3.950 4.725 5.500 resistance vs. supply voltage ds3901 toc08 supply voltage (v) resistance change (%) resistor setting = 7fh r2 r0 r1 47 59 51 49 55 53 57 0 2.75 5.50 resistance vs. power-up supply voltage ds3901 toc09 supply voltage (v) resistance (k ? ) resistor setting = ffh > 1m ? r0 47 59 51 49 55 53 57 0 2.75 5.50 resistance vs. power-down supply voltage supply voltage (v) resistance (k ? ) ds3901 toc10 resistor setting = ffh > 1m ? r0 -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r0 absolute linearity vs. resistor setting ds3901 toc11 setting (dec) absolute linearity (lsb) -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r0 relative linearity vs. resistor setting ds3901 toc12 setting (dec) relative linearity (lsb) -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r1 absolute linearity vs. resistor setting ds3901 toc13 setting (dec) absolute linearity (lsb) -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r1 relative linearity vs. resistor setting ds3901 toc14 setting (dec) relative linearity (lsb)
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 6 _____________________________________________________________________ pin description pin name function 1 scl i 2 c clock input 2 sda i 2 c data i/o pin 3 add_sel i 2 c slave address select pin 4 bk_sel bank select pin. this pin has an internal pulldown resistor, r bk . 5 dis high-impedance disable input. this pin has an internal pullup resistor, r dis . 6, 13 n.c. no connection 7 gnd ground 8 l0 resistor 0 low terminal 9 h0 resistor 0 high terminal 10 h1 resistor 1 high terminal 11 l2 resistor 2 low terminal 12 h2 resistor 2 high terminal 14 v cc voltage supply typical operating characteristics (continued) (v cc = +3.3v, t a = +25 c, unless otherwise noted.) -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r2 absolute linearity vs. resistor setting ds3901 toc15 setting (dec) absolute linearity (lsb) -0.75 0.65 0.45 0.25 0.05 -0.15 -0.35 -0.55 0 51 102 153 204 255 r2 relative linearity vs. resistor setting ds3901 toc16 setting (dec) relative linearity (lsb)
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom _____________________________________________________________________ 7 v cc configuration memory i 2 c interface 84h 88-8bh sda scl add_sel data bus address control hi-z1 control hi-z2 hi-z1 hi-z0 l0_sw r0 50k ? fs 256 positions hi-z2 control mux control mux bank 0 bank 1 hi-z0 control r bk r dis 8fh 90-93h 94-97h 98h 99h 9ah 9ch 9dh 9eh 9fh password entry (sram) status (sram) pw1 password setting pw2 password setting resistor 0 bank 0 resistor 1 bank 0 resistor 2 bank 0 resistor 0 bank 1 resistor 1 bank 1 resistor 2 bank 1 i 2 c slave address pw1 eeprom v cc v cc gnd dis bk_sel h0 l0 h1 h2 l2 pw2 eeprom r1 30k ? fs 256 positions r2 20k ? fs 256 positions ds3901 block diagram
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 8 _____________________________________________________________________ detailed description the ds3901 contains three configurable variable resis- tors. the block diagram illustrates the features of the ds3901. the following sections discuss these features in detail. dual bank resistor settings the setting for each resistor can be loaded from one of two possible registers. these registers are referred to as banks with each resistor having a bank 0 and bank 1 value. the bank to be loaded as the resistor value is selected by the or ing of the bk_sel pin logic state and the bsc control bit (bit 3, register 84h). see the memory map section for details. if the result of the or ing is a 0, then all three resistors will use the values stored in their bank 0 locations. if the result is a 1, then all three resistors will use the values stored in their bank 1 locations. shunt resistor switch resistor 0 has the option to have an external fixed resis- tor connected to the l0 pin. this provides a means to select between a standard full-scale resistor value and an extended full-scale value. by default, the l0_sw bit (bit 4 of the configuration register, 84h) is set to a value of 0. when the l0_sw bit is 0, the internal connection from the low side of resistor 0 to ground is opened, and the low terminal of resistor 0 is only connected to the l0 pin. this allows for an external resistor to be attached to the l0 pin for an extended full-scale value. by writing the switch control bit l0_sw to a 1, the low terminal of resistor 0 is internally connected to ground. high-impedance function there are two ways to place the resistors in a high- impedance (hi-z) state. one way is to set the dis pin to a 1. this is done by either floating the pin (there is an internal pullup resistor, r dis ) or by connecting dis directly to v cc . when the dis pin is held high or left floating, all three resistors are held in a high-impedance state. the second method is to use bits 0 to 2 of the configuration register (84h), to set each resistor to a high-impedance state (see the memory map section for details). the state of the dis pin overrides the state of the high-impedance control bits (see the memory map section for details). slave address byte the add_sel pin is used to select the i 2 c address of the ds3901. when the add_sel pin is connected low, the i 2 c address of the ds3901 is a2h. when the add_sel pin is connected high, the value stored in the slave address register (9fh) is used. the default value for the slave address register is shown in the memory map section. the slave address register can be pro- grammed to one of 128 possible addresses since the lsb of the slave address register is reserved as the read/write bit for the i 2 c command structure. password protection the memory of the ds3901 is write-protected with a two-level password scheme. all memory locations can be read without a password, with the exception of the password entry registers and password setting regis- ters. once the appropriate password is entered in the password entry bytes (88 to 8bh), the ds3901 will allow write access to the memory areas designated for that password. the setting for the pw1 password is written in the pw1 password setting register (bytes 90 to 93h). the setting for the pw2 password is written in the pw2 password setting register (bytes 94 to 97h). see the memory map section for more details. entering the pw2 password allows access to areas protected by the pw1 password. when shipped from the factory, both password settings are all zeroes. likewise, every time the device is pow- ered up the password entry register (sram) defaults to all zeroes. if write protection is not desired, leave the password setting at the factory default and ignore the password entry register. write protection goes into effect once either or both default password settings have been changed to unique values.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom _____________________________________________________________________ 9 memory map the memory consists of 256 bytes and is write-protected with a two-level password scheme. table 1 below shows how the memory map is organized. register details are discussed in the register descriptions section. table 1. memory map access description addr binary msb lsb factory default no pw pw1 pw2 type lower memory 00 7fh pw2 eeprom 00h r r r/w eeprom memory 80 83h pw1 eeprom 00h r r/w r/w eeprom configuration 84h l0_sw bsc hiz2 hiz1 hiz0 00h r r/w r/w eeprom memory 85 87h pw1 eeprom 00h r r/w r/w eeprom password entry 88 8bh msb lsb 00h w w w sram memory 8c 8eh sram 00h r/w r/w r/w sram status 8fh 0 0 0 bss 0 0 0 diss 000x000xb r r r sram password setting pw1 90 93h msb lsb 00h w eeprom password setting pw2 94 97h msb lsb 00h w eeprom resistor 0 bank 0 98h 7fh r r r/w eeprom resistor 1 bank 0 99h 7fh r r r/w eeprom resistor 2 bank 0 9ah 7fh r r r/w eeprom memory 9bh pw2 eeprom 00h r r r/w eeprom resistor 0 bank 1 9ch 7fh r r r/w eeprom resistor 1 bank 1 9dh 7fh r r r/w eeprom resistor 2 bank 1 9eh 7fh r r r/w eeprom slave address 9fh i 2 c slave address a0h r r r/w eeprom memory a0h ffh pw2 eeprom 00h r r r/w eeprom memory registers 00h 7fh: pw2 eeprom factory default: 00h access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 00h 7fh eeprom register descriptions
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 10 ____________________________________________________________________ memory registers 80h 83h: pw1 eeprom factory default: 00h access without password: read only access with pw1 password: read and write access with pw2 password: read and write memory type: nonvolatile (eeprom) 80h 83h eeprom memory register 84h: configuration register factory default: 00h access without password: read only access with pw1 password: read and write access with pw2 password: read and write memory type: nonvolatile (eeprom) l0_sw bsc hiz2 hiz1 hiz0 84h b7 b0 bits 7 5 these bits are set to 0. bit 4 l0_sw: selectable switch (see the block diagram ) that allows for an external shunt resistor to be connected to the l0 pin. 0 = switch l0_sw is open (default). 1 = switch l0_sw is closed. bit 3 bsc: a control bit that, when or d with the state of the bk_sel pin, selects which bank of registers will be used to determine the setting of resistors 0, 1, and 2. 0 = bk_sel pin determines which bank settings are used. 1 = bank 1 settings are used. bit 2 hiz2: a control bit used to select a high-impedance state for resistor 2. if the dis pin is high, all resistors are high impedance regardless of hi-z control pin state. if the dis pin is low, then the following is true: 0 = resistor 2 is not in a high-impedance state (default). 1 = resistor 2 is placed in a high-impedance state. bit 1 hiz1: a control bit used to select a high-impedance state for resistor 1. if the dis pin is high, all resistors are high impedance regardless of hi-z control pin state. if the dis pin is low, then the following is true: 0 = resistor 1 is not in a high-impedance state (default). 1 = resistor 1 is placed in a high-impedance state. bit 0 hiz0: a control bit used to select a high-impedance state for resistor 0. if the dis pin is high, all resistors are high impedance regardless of hi-z control pin state. if the dis pin is low, then the following is true: 0 = resistor 0 is not in a high-impedance state. (default) 1 = resistor 0 is placed in a high-impedance state.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ____________________________________________________________________ 11 there are two passwords for the ds3901, the pw1 password and the pw2 password. the memory map register descriptions indicate the type of access granted for each level of password used. see the password protection section for details on password access. memory registers 85h 87h: pw1 eeprom factory default: 00h access without password: read only access with pw1 password: read and write access with pw2 password: read and write memory type: nonvolatile (eeprom) 85h 87h eeprom memory registers 88h-8bh: password entry factory default: 00000000h access without password: write only access with pw1 password: write only access with pw2 password: write only memory type: volatile (sram) 88h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 89h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 8ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 8bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 memory registers 8ch 8eh: sram factory default: 00h access without password: read and write access with pw1 password: read and write access with pw2 password: read and write memory type: volatile (sram) 8ch-8eh sram
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 12 ____________________________________________________________________ memory register 8fh: status factory default: 000x000xb access without password: read only access with pw1 password: read only access with pw2 password: read only memory type: volatile (sram) 8fh 0 0 0 bss 0 0 0 diss b7 b0 bits 7 5 these bits are 0. bit 4 bss: a status bit that indicates the state of the bk_sel pin. 0 = bk_sel pin is low. 1 = bk_sel pin is high. bits 3 1 these bits are 0. bit 0 diss: a status bit that indicates the state of the dis pin. 0 = dis pin is low. hi-z control bits can be used to select high-impedance state for each resistor. 1 = dis pin is high. all resistors are in a high-impedance state. memory registers 90h 93h: pw1 password setting factory default: 00000000h access without password: none access with pw1 password: none access with pw2 password: write only memory type: nonvolatile (eeprom) 90h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 91h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 92h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 these four bytes contain the password used to access memory that is protected by the pw1 password.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ____________________________________________________________________ 13 memory registers 94h 97h: pw2 password setting factory default: 00000000h access without password: none access with pw1 password: none access with pw2 password: write only memory type: nonvolatile (eeprom) 94h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 95h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 96h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 97h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b 7 b0 these four bytes contain the password used to access memory that is protected by the pw2 password. memory register 98h: resistor 0, bank 0 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 98h b7 b0 this register contains the bank 0 values for resistor 0. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 0 bank 0 or resistor 0 bank 1 is used for the resistor 0 setting. see the configuration register in register 84h for logic details.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 14 ____________________________________________________________________ memory register 99h: resistor 1, bank 0 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 99h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 this register contains the bank 0 values for resistor 1. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 1 bank 0 or resistor 1 bank 1 is used for the resistor 1 setting. see the configuration register in register 84h for logic details. memory register 9ah: resistor 2, bank 0 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9ah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 this register contains the bank 0 values for resistor 2. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 2 bank 0 or resistor 2 bank 1 is used for the resistor 2 setting. see the configuration register in register 84h for logic details. memory register 9bh: pw2 eeprom factory default: 00h access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9bh eeprom
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ____________________________________________________________________ 15 memory register 9ch: resistor 0, bank 1 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 this register contains the bank 1 values for resistor 0. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 0 bank 0 or resistor 0 bank 1 is used for the resistor 0 setting. see the configuration register in register 84h for logic details. memory register 9dh: resistor 1, bank 1 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 this register contains the bank 1 values for resistor 1. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 1 bank 0 or resistor 1 bank 1 is used for the resistor 1 setting. see the configuration register in register 84h for logic details. memory register 9eh: resistor 2, bank 1 factory default: 7fh access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 this register contains the bank 1 values for resistor 2. the or d result of the state of the bsc bit (bit 3, 84h) and the bk_sel pin determines if resistor 2 bank 0 or resistor 2 bank 1 is used for the resistor 2 setting. see the configuration register in register 84h for logic details.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 16 ____________________________________________________________________ memory register 9fh: slave address register factory default: a0h access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) 9fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7 b0 the i 2 c slave address of the ds3901 depends on the state of the add_sel pin. if this pin is low, then the slave address is fixed at a2h. if the add_sel pin is high, then the slave address is determined by the value stored in eeprom at address 9fh. factory default value for the slave address is a0h. the seven most sig- nificant bits are used (the lsb is not used because it is in the bit position of the r/w bit) to allow the slave address to be programmed to one of 128 possible addresses. memory registers a0h ffh: pw2 eeprom factory default: 00h access without password: read only access with pw1 password: read only access with pw2 password: read and write memory type: nonvolatile (eeprom) a0h ffh eeprom
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ____________________________________________________________________ 17 sda scl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf note: timing is reference to v il(max) and v ih(min) . figure 1. i 2 c timing diagram i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and their logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see the timing dia- gram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans- fer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold-time requirements (see figure 1). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 1) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 1) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom 18 ____________________________________________________________________ byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (msb first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowl- edgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (msb first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the add_sel pin and slave address register (9fh) determine the i 2 c slave address for the ds3901. if add_sel is low, then the slave address is fixed at a2h. if add_sel is high, then the slave address in the slave address register (9fh) is used. the lsb of the slave address byte is the r/ w bit. if the r/ w bit is 0, then the master indicates it will write data to the slave. if r/ w = 1, then the master will read data from the slave. if an incorrect slave address is written, the ds3901 will assume the master is communicating with another i 2 c device and ignore the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave s acknowl- edgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave the master generates a start condi- tion, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the ds3901 is capable of writing up to 8 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page. attempts to write to additional pages of memory without sending a stop condition between pages result in the address counter wrapping around to the beginning of the present row. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, and then wait for the bus free or eeprom write time to elapse. then the master may generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom page is written, the ds3901 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds3901, which allows the next page to be written as soon as the ds3901 is ready to receive the data. the alternative to acknowledge polling is to wait for a maxi- mum period of t w to elapse before attempting to write again to the device. eeprom write cycles: when eeprom writes occur, the ds3901 will write the whole eeprom memory page even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. the ds3901 s eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature.
ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom ____________________________________________________________________ 19 reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the mas- ter generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte, it nacks to indicate the end of the transfer and generates a stop condition. this can be done with or without modifying the address counter s location before the read cycle. applications information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01f or a 0.1f capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the ds3901 that requires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be uti- lized for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the ac electrical characteristics are within specification. chip topology transistor count: 52,353 substrate connected to ground
package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . v cc v cc h2 in+ vref th modset apcset laser driver limiting amp in- differential data in l2 bk_sel add_sel sda (optional shunt resistor) scl h1 h0 l0 gnd 4.7k ? 50k ? 50k ? 2.5k ? 4.7k ? signals from host dis 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f v cc max3738 max3747a ds3901 typical operating circuit ds3901 triple, 8-bit nv variable resistor with dual settings and user eeprom maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation.

▲Up To Search▲

Price & Availability of DS3901E

	To Download DS3901E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .